1. Field
This invention relates to data buffers and, more particularly, to data buffers that connect a wide input bus to a narrow output bus.
2. Background Information
A plurality of digital signals can be presented simultaneously on a plurality of lines making up a parallel bus. In some applications, data may be presented on a wide bus and then transferred to a narrower bus for use by remaining portions the system. For example, a Rambuse(copyright) memory controller presents 128 bits of data, 2 quad words, which must be narrowed to 64 bits, one quad word, for use by the remaining portions of the system.
The conversion between a wide input bus and a narrow output bus that is one-half the width of the wider bus is relatively straightforward if the data is presented in a consistent order. Unfortunately, this is not always the case. Consider a system that uses data elements of a given width (number of bits) that are received from a source that can provide data units containing two data elements on a wide input bus. Each data unit consists of a first data element and a second data element. A buffer is required to couple the wide input bus to a narrow output bus of one-half the width of the input bus. The buffer must also interleave the two data elements of each data unit in the correct order.
If the input bus consists of an A lane and a B lane, each lane can present one of the two data elements for a data unit. In one cycle, lane A might present the first data element and lane B lane the second. A later cycle might have a reversed presentation. Thus, the buffer must be capable of selectively interleaving in an xe2x80x9cA then Bxe2x80x9d order and in a xe2x80x9cB then Axe2x80x9d order. Another possibility is one of the two lanes presenting data with the other lane left unused. The second data element would appear in a later cycle on the other lane. Presentation of the data in two cycles will be termed a non-aligned presentation of the data. It is possible that several non-aligned presentations occur in successive cycles. In the first cycle, the first data element of a first data unit might be presented on the B lane of the input bus. In the following cycle, the second data element of the first data unit could be presented on the A lane of the input bus. Simultaneously, the first data element of a second unit could be presented on the B lane of the input bus. This could continue until a cycle in which one data element is presented, which would be the second data unit and which would appear on the A lane of the input bus. Table 1 shows the possible data presentations. Idle cycles where no data is presented can occur between any two active cycles of any form of presentation. The desired order on the output bus is first element of first unit, second element of first unit, first element of second unit, and so on. The buffer that connects the wide input bus to the narrow output bus must receive any of five types of input cycles and produce the desired order on the output bus.
One way to accomplish this would be to reorder data received on the input bus necessary so that all the data elements are buffered as required by the output bus. However, this requires a two to one multiplexer for every line of the wide input bus connected to selectively exchange the two halves of the input bus. For a very wide input bus the number of circuits required can be substantial. Accordingly, what is required is a method and apparatus for receiving data units on a wide input bus with varying data element orders, buffering the data, and correctly presenting the data elements on a narrow output bus without requiring a multiplexer for every line of the input bus.
A buffer circuit coupling an input bus having a first portion and a second portion to an output bus. Each of the first portion, the second portion, and the output bus carry data of a predetermined width. The buffer circuit comprises a first plurality of registers, a second plurality of registers, an unload counter, and a multiplexer. The first plurality of registers is coupled to store data from the first portion of the input bus. The second plurality of registers is coupled to store data from the second portion of the input bus and from a data order signal. The unload counter provides an unload count that selects one of the first plurality of registers and a corresponding one of the second plurality of registers. The multiplexer provides either the selected one of the first plurality of registers or the corresponding one of the second plurality of registers to the output bus. The multiplexer is responsive to the data order signal stored in the corresponding one of the second plurality of registers.